Analog-to-Digital Converter (ADC or A/D Converter)

The signals of the natural environment, such as voice, temperature, light ... and so on, are continuous-time and continuous-amplitude variable (analog) signals. Analog signals have infinite states available. But, the computers we are using are digital signal systems. Digital signals have two states — on (1) or off (0). The analog signals need to be converted into a digital representation which can then be stored in a computer for further processing. An A/D Converter is a device that converts analog signals (usually voltage) obtained from environmental phenomena into digital format. In other words, ADC digitizes an analog signal by converting data with infinite states to a series of pulses. The amplitudes of these pulses can only achieve a finite number of states.

BasicFunctionOfADC s
Figure 1: Basic Function of ADC

ADCs have the following key characteristics:

Input range, or Full-Scale input Range, measured in Volts, is the range of voltages that can be applied at the input of the ADC.
Output range, or quantization, measured in bits, is the number of bits in each output sample (typical values are 8, 12, 16, 24, and 32). It is common to say an "8-bit ADC", meaning an ADC with output samples that are 8-bit wide.
The sampling rate, measured in Hz, is the rate at which the ADC generates its output samples.

ADC Specifications

Full-Scale Input Range

The full-scale input of an ADC is the largest signal amplitude that can be delivered to the converter before the signal is clipped in its digital output representation.

**Sampling Rate (f_s)**

The sampling rate is the frequency expressed in Hertz (Hz) at which the ADC samples the input analog signal.

The Nyquist Theorem (or Shannon Theorem) states that an analog signal with the highest frequency of f_a MUST be sampled at a sampling rate f_s > 2 f_a to avoid loss of information.

If f_s < 2 f_a then phenomena called aliasing will occur in the analog signal bandwidth.

Resolution

There are two types of resolution in the A/D Conversion: bit-resolution and voltage-resolution.

The bit resolution of an ADC refers to the number of bits in the digital output code of the ADC.
The voltage resolution is the minimum change in input voltage which can be resolved by the ADC. It is the same as analog quantization size.

Voltage-Resolution, (or Quantization, Least Significant bit Voltage)

The voltage resolution represents the minimum change in voltage that is required to guarantee a change in the output code level. It is also called the least significant bit voltage. The quantization of ADC (Q) is equal to the voltage resolution (or the LSB voltage).

The voltage resolution of an ADC is equal to its overall voltage measurement range divided by the total numbers of digital output:
Resolution_Voltage = Q = V_LSB = (V_Ref,max - V_Ref,min) / 2ⁿ = V_FSR / 2ⁿ -------- (1)

If you are using an 8-bit ADC, and the voltage input range of the ADC is from 0 to 5 volts. An 8-bit digital value can represent 256 (2⁸ = 256) different numbers. In this example, the bit-resolution of the ADC is 8-bit, and it has a voltage resolution of 20mV (10v/256).

The Ideal Transfer Function for A/D Conversion

The transfer function of an ADC is a plot of the voltage input to the ADC versus the code's output by the ADC. The horizontal axis represents a continuous analog input signal. The vertical axis shows the digital output codes which can be thought of as a level for rounding off the analog input signal to its nearest digital equivalent. The full-scale input range of the ADC is equally divided over the total number of digital output codes to transform the dashed red line into the staircase blue line as shown in Figure 2.

TheIdealTransferFunctionOfADC s
Figure 2: Ideal Transfer Function of a 4-bit ADC

The number of bits is the number of binary digits in the digital output code used to represent the full-scale analog signal. In this example, we have 4-bit or binary digits ADC, so N = 4, and the number of codes here is 2⁴ = 16, which corresponds to counting from binary 0000 to 111 which is 0 to 15 in decimal, Here, we assume the output of the ADC is linear.

N: the number of bits ADC
V_FSR: the Full-Scale input Range of the ADC
V_LSB: the minimum resolvable voltage, or ADC voltage resolution

\(\begin{array}{lllllllllllllll} {NumberofCodes = {2^N}}\\ {Resolutio{n_{bit}} = N}\\ {Resolutio{n_{Voltage}} = Q = {V_{LSB}} = \frac{{{V_{FSR}}}}{{{2^N}}}} \end{array}\)

The full-scale input range in this example is 2V (0 to 2 V). The voltage resolution is often identified as the width of the least significant bit, it can be computed by taking the full-scale range and dividing by the total number of bits, or 2 to the N power. Therefore, the least significant bit width or voltage resolution can be calculated by dividing 2V by 16 to get a resolution of 0.125V.

\(N = 4\)

\({V_{FSR}} = 2V - 0V = 2V\)

\({V_{LSB}} = \frac{{{V_{FSR}}}}{{{2^N}}} = \frac{{2V}}{{{2^4}}} = 0.125V\)

The full-scale range in this example is 2V, but the maximum detectable input voltage is the full-scale range minus one LSB or 1.875V in this example.

Math Conversion Equations

The A/D Converter samples the analog signal and then provides a quantized digital code to represent the input signal. The digital output codes get post-processed and results can be reported to an operator who will use this information to make decisions and take actions. Therefore, it is important to correctly relate the digital codes back to the analog signals they represent.

In general, the ADC input voltage is related to the output code by a simple relationship, as shown in Equation 1:

\({V_m} = {D_{out}} \times {V_{LSB}}\) ---------- (2)

where V_m (V) is the ADC's input voltage or the measured voltage; D_out is the ADC's digital-output code in decimal format, and V_LSB is the voltage resolution or the value of the least significant bit in the ADC code.

Equation 1 is a general equation that can work for any ADC. It doesn't matter if the ADC's output code is in straight binary or two's complement format, as long as the binary number is correctly converted to its equivalent decimal value.

Example 1

Example 2

Example 3

From here, it is necessary to look at specific ADC architectures in order to determine the best ADC for the job. This includes:

SAR (Successive Approximation Register) ADCs
Flash ADCs
Delta-Sigma ADCs

SAR ADC

SAR ADC is the most commonly used method. It has a smaller chip area and lower power consumption analog-to-digit conversion. It is frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 mega samples per second (MSPS). Bit resolution for SAR ADCs most commonly ranges from 8 to 16 bits. These features make the SAR ADCs especially suitable for the following applications:

Wearable, handheld, and sensor devices
Magnetic card reader
High-speed data collection
Power meter
Pulse oximeter

SAR ADC Architecture

The SAR ADC basically implements a binary search algorithm. There are many variations for implementing a SAR ADC, but the basic architecture is simple. The SAR ADC circuit typically consists of four chief sub-circuits, and it is shown in Figure 3.

Figure 3: Simplified N-bit SAR ADC Architecture

A sample and hold circuit to acquire the input analog voltage (V_adc).
An analog voltage comparator that compares V_in to the output of the internal DAC (V_DAC) and outputs the result of the comparison to successive approximate register (SAR logic).
A successive approximate register subcircuit was designed to supply an approximate digital code for V_in to the internal DAC.
An internal reference DAC that, for comparison with V_REF, supplies the comparator with an analog voltage equal to the digital code output of the SAR logic.

Basic Operation of the SAR ADC

The SAR ADC does the following steps for each sample:

The analog input voltage (V_adc) is sampled and held.
To implement the binary search algorithm, the N-bit register is first set the MSB to 1 (that is 1000 ... 00₂). This will set the DAC output (V_DAC) to be V_ref / 2, where V_ref is the reference voltage provided to the ADC.
A comparison is then performed to determine if V_in is less than, or greater than, V_DAC.
- If V_in is greater than V_DAC, the comparator output is logic 1, and the MSB of the N-bit register remains at 1.
- Conversely, if V_in is less than V_DAC, the comparator output is a logic low and the MSB of the register is cleared to logic 0.
The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB.
Once all bits have been approximated, the N-bit digital approximation is output at the end of the conversion (EOC).

Figure 4: SAR Operation (3-bit ADC Example)

Figure 4 shows an example of a 3-bit conversion. The y-axis represents the V_DAC voltage. Let us focus on the V_in1 = 6.25 V in the example, the first comparison sets the MSB of the register to 100₂, and the comparison shows that V_in1 < (V_DAC = V_ref / 2). Thus, bit 2 is set to 0. The register is then set to 010₂ and the second comparison is performed. As V_in1 < (V_DAC = Vref / 4). Bit 1 is set to 0, and the register is then set to 001₂ for the final comparison. Finally, bit 0 is set to 0 because V_in1 < (V_DAC = Vref / 8). The digital result for V_in1 is 000₂.

Notice that a 4-bit ADC requires three comparison cycles. In general, an N-bit SAR ADC will require N comparison cycles and will not be ready for the next conversion until the current one is complete. This explains why these ADCs are power - and space-efficient.