FPGA Lab 02: Combinational Logic (Comparator/Decoder/Encoder)

Step 1: Design a 2-bit Comparator

1. Truth Table Creation:
   • Create a truth table for the 2-bit comparator with inputs
   • Outputs are GT (Greater Then), EQ (Equal), and LT (Loess Then).
2. Karnaugh Maps (K-Maps):
   • Based on the truth table, draw K-maps for each output (GT, EQ, LT).
   • Simplify the Boolean expressions using K-map techniques.
3. Boolean Expressions:
   • Derive simplified Boolean expressions for GT, EQ, and LT from the K-maps.
4. Verilog Code for 2-bit Comparator:
   • Implement the Boolean expressions in Verilog.

5. Draw the logic circuits for the two-bit comparator with outputs GT, EQ, and LT.
6. Implement the two-bit comparator using Gate-Level modeling in Verilog.
   

   module comparator_2bit (a1, a0, b1, b0, gt, eq, lt);
   input  a1, a0, b1, b0;
   output gt, eq, lt;
   
   
   // Your code here
   
   
   endmodule
   

...

6. A 4-bit comparator will use 4-bit input A and 4-bit input B. Therefore, the function table of the 4-bit comparator is shown below.
   
7. Since the 4-bit comparator is built by using two 2-bit comparators to compare higher 2-bit of input A and B and lower 2-bit of A and B, the function table based on the previous 4-bit function table can be built as below:

   G1	E1	L1	G0	E0	L0	GT	EQ	LT

   
   GT =
   EQ =
   LT =
8. Complete the cmp_4bit.v module as the following block diagram.
   
9. Compile the code and check the RTL Viewer. If there are no errors, program and test the code to the FPGA board.
10. Use the following table to test your system.
    

    A SW[7:4]	B SW[3:0]	GT LEDR[2]	EQ LEDR[1]	LT LEDR[0]