**FPGA Lab 05: Binary Adder/Subtractor, and Decimal Adder**

**Objectives**

- Design of 4-bit adder/subtractor using hierarchical gate-level modeling

**Required Reading Material**

- Textbook:
, 6th edition, Mano and Ciletti, ISBN-13: 978-0-13-454989-7**Digital Design: with An Introduction to the Verilog HDL, VHDL, and SystemVerilog**

Ch 4.5

**Background Information**

You will to first learn how to run the Quartus Prime synthesis tool to compiler your hardware design to a file that can be downloaded and run on the FPGA. Work through this Lesson 01: Create a New FPGA Project using Quartus Prime Standard to learn how this is done. You will be doing this compilation many times during the rest of the labs, so you might as well take your time and understand how it works.

**Designing with Verilog**

In this lab, you will convert schematics into Verilog modules to build a relatively complex design. Verilog is a hardware description language. Although it may look like a programing language, Verilog is used to describe the functionality of the hardware. Verilog programs are not actually executed by hardware like C or Java programs; instead, they are turned into the hardware circuit described by Verilog code. Your design will be comprised of several modules that will be connected together using structural modeling in Quartus.

#### 1. Start with a 1-bit Full-Adder

**1-bit Full-Adder Design**

A 1-bit full-adder has three binary inputs and two binary outputs:

**Inputs**:

Two of the inputs are the two significant bits to be added of numberand number**a**. And the third input**b**(Carry-In) is the carry from the previous lower significant position.**c**_{in}**Outputs**:

The two outputs are theand**sum**(Carry-out).**c**_{out}**Formula**:

\([cout, sum] = cin = a + b\)

Fill in the truth table for the full-adder listed in Table 1.1 with the formula \([cout,s] = cin + a + b\). Then, using K-maps to simplify the Boolean equations for output ** cout** and

*. Write down your final equations in SOP or POS format.*

**sum****Table 1.1**: Full-Adder

cin | a | b | cout | sum |
---|---|---|---|---|

0 | 0 | 0 | ||

0 | 0 | 1 | ||

0 | 1 | 0 | ||

0 | 1 | 1 | ||

1 | 0 | 0 | ||

1 | 0 | 1 | ||

1 | 1 | 0 | ||

1 | 1 | 1 |

K-Map for **cout**

cout |
a b |
||||

00 | 01 | 11 | 10 | ||

cin |
0 | 0 |
1 |
3 |
2 |

1 | 4 |
5 |
7 |
6 |

cout =

K-Map for **sum**

sum |
a b |
||||

00 | 01 | 11 | 10 | ||

cin |
0 | 0 |
1 |
3 |
2 |

1 | 4 |
5 |
7 |
6 |

sum =

**The Circuit of a 1-bit Full-Adder**

According to the Boolean expressions, draw the circuit of the * sum* and

*by using logical gates:*

**c**_{out}**AND**,

**OR**,

**XOR**, and

**NOT**gates in

*schematic 01*. And also define all connection wires with a unique net name.

**Schematic 01**: the Circuit of a 1-bit Full-Adder

#### 2. 4-bit Binary Adder

**4-bit Binary Ripple Carry Adder with Overflow Detection**

In this part, you will design a 4-bit full adder whose port list was defined in Figure 1.2. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain.

**Figure 1.2**: I/O Ports for Top of the 4-bit Full Adder

The addition of 4-bit numbers requires a chain of 4 full adders, and the input carry (**C0**) to the least significant position must be fixed at 0. Figure 1.3 shows the connection of 4 full-adders circuits to provide a 4-bit binary ripple carry adder.

**Figure 1.3**: 4-bit Full Adder with Overflow Detection

#### 3. 4-bit Binary Adder-Subtractor

**Build Subtractor using Adder**

The subtraction of unsigned binary numbers can be done by taking the 2's complement of * B* and adding it to

*. The 2's complement can be obtained by taking the 1's complement and adding 1 to the least significant pair of bits. The 1's complement can be implemented with inverters, and a 1 can be added to the sum through the input carry of a full adder.*

**A**\[A - B = A + ( - B) = A + (\overline B + 1)\]

By preceding each * b* input bit on the adder with a 2-to-1 multiplexer (MUX) as shown below.

- When \(invB = 0\), the MUX connects the output pin to input 0, so \({b_{in}} = b\).
- When \(invB = 1\), the MUX connects the output pin to input 1, therefore \({b_{in}} = \overline b \)

As you can see from the truth table results above, an **XOR** gate can be used to mark number * b* as positive or negative without using a multiplexer.

To allow the adder to perform addition and subtraction, the control input * invB* must be connected to the input carry (

*C0*) and the name changed to

*.*

**Sub**- Addition when
**Sub = 0**⇒ \(C0 = 0\) and \(Bin = B\), ∴ \([C4,Sum] = A + Bin + C0 = A + B + 0 = A + B\) - Subtractor when
**Sub = 1**⇒ \(C0 = 1\) and \(Bin = \overline B\), ∴ \([C4,Sum] = A + Bin + C0 = A + \overline B + 1 = A - B\);

**Figure 1.4**: 4-bit Adder-Subtractor with Overflow Detection

**Experiments**

#### Accordion

- Create a folder on your
- Start
**Quartus Prime**, and select "".*New Project Wizard*- On the next page ("Directory, Name, Top-Level Entity"), choose the directory create a new project, store this project to a new folder named "
*Lab01_1_BinaryAddSub*"; set project name as "**binaryAddSub**" and the top-level module name as "binaryAddSub_top".

- On the next page ("Directory, Name, Top-Level Entity"), choose the directory create a new project, store this project to a new folder named "
- Create a new Verilog HDL file, using the following template code to implement your 1-bit full-adder design into Verilog using gate-level modeling.
- Create a new Verilog HDL file, using the following template code to implement a 4-bit full adder with overflow detection by connecting four 1-bit full-adder modules.