FPGA Lab 11: Behavioral Modeling
This laboratory introduces the behavioral modeling style in Verilog. Students will learn how to describe digital logic by using always blocks and common procedural statements such as if, case, and for. The lab also emphasizes the distinction between combinational and sequential logic, which is essential for later topics such as finite state machines and memory design.
Learning Objectives
- Understand the concept of behavioral modeling in Verilog.
- Distinguish among structural, dataflow, and behavioral modeling styles.
- Use always blocks for combinational and sequential logic.
- Use if, case, and for statements in synthesizable Verilog.
- Apply correct coding rules for FPGA-oriented RTL design.
- Verify behavioral designs using simulation.
Background
1. What is Behavioral Modeling?
Behavioral modeling describes what a circuit does rather than explicitly showing how it is built from gates. This style is especially useful for writing register-transfer level (RTL) designs in FPGA development.
2. Common Verilog Modeling Styles
| Modeling Style | Description | Typical Example |
|---|---|---|
| Structural | Describes circuits using gates or lower-level modules. | AND, OR, NOT gate instantiation |
| Dataflow | Describes logic using continuous assignments. | assign y = a & b; |
| Behavioral | Describes circuit behavior using procedural blocks. | always @(*), always @(posedge clk) |
3. Two Important Types of always Blocks
Combinational logic:
always @(*) begin
// combinational logic
end
Sequential logic:
always @(posedge clk) begin
// sequential logic
end
Important Design Rules
- Rule 1: Assign all outputs in combinational logic
- Rule 2: Use clock edges for sequential logic
- Rule 3: Use '=' for combinational and '<=' for sequential
- Rule 4: Use reset to initialize sequential logic
- Rule 5: Avoid unintended latch inference
Lab Experiments
Exp 01: 4-bit Comparator Using Behavioral Modeling
4-bit Comparator Using Behavioral Modeling
Design a 4-bit comparator that compares inputs A and B. The outputs are: gt for A > B, eq for A = B, and lt for A < B. Use an always @(*) block and implement the logic with if and else if.
| A | B | gt | eq | lt |
|---|---|---|---|---|
| 5 | 3 | 1 | 0 | 0 |
| 4 | 4 | 0 | 1 | 0 |
| 2 | 6 | 0 | 0 | 1 |
Exp 02: 7-Segment Decoder Using case Statement
7-Segment Decoder Using case Statement
Design a behavioral 7-segment decoder that converts a 4-bit input value into the corresponding 7-segment display pattern. For the DE10-Lite board, the 7-segment display is active-low, so the segment outputs must follow active-low logic. Use a case statement and include a default case.
default: seg = 7'b1111111;Exp 03: 4-bit Register with Enable
4-bit Register with Enable
Design a 4-bit register with an enable input. On each positive edge of the clock, if en = 1, the register loads the input data d. If en = 0, the register holds its current value. Use an always @(posedge clk) block and non-blocking assignment.
| Clock Edge | en | q(next) |
|---|---|---|
| posedge | 1 | d |
| posedge | 0 | hold |
Exp 04: 4-bit Up Counter
4-bit Up Counter
Design a 4-bit up counter using behavioral modeling. The counter increments by 1 on every positive edge of the clock. When the reset signal is asserted, the counter returns to 0. Use a synchronous reset unless your instructor specifies otherwise.
Expected counting sequence: 0 → 1 → 2 → ... → 15 → 0
Exp 05: 8-bit Parity Generator Using for Loop
8-bit Parity Generator Using for Loop
Design an 8-bit even parity generator using a behavioral for loop. The output parity bit should make the total number of logic 1s even.
Simulation Requirement
All designs must be verified by simulation before hardware implementation. Students should write a corresponding testbench for each task, apply test vectors, and confirm the expected results using waveform observation.
- Create a Verilog testbench for each design.
- Apply representative input patterns.
- Observe output changes in the waveform viewer.
- Confirm that the circuit behavior matches the design specification.
Required Deliverables
- Verilog source code for each task
- Testbench file for each task
- Simulation waveform screenshots
- A short explanation of the design and verification results
Common Mistakes
- Not assigning all outputs in a combinational always @(*) block
- Inferring unwanted latches
- Using blocking assignment in sequential logic
- Forgetting the default branch in a case statement
- Writing simulation-only code that is not synthesizable
- Mixing combinational and sequential logic incorrectly in the same design block
Discussion Questions
- What is the difference between structural, dataflow, and behavioral modeling?
- Why must all outputs be assigned in a combinational always block?
- Why is non-blocking assignment recommended for sequential logic?
- What is the purpose of the default branch in a case statement?
- Why is simulation necessary before downloading the design to the FPGA board?
Conclusion
In this lab, students practice behavioral modeling as a major step from basic logic design toward RTL-based digital system design. The concepts in this experiment will be used directly in later topics such as finite state machines, memory blocks, and larger FPGA systems.