Lesson KB 06: Understanding the SDC File in FPGA Design

Altera MAX-10 Lite (10M50DAF484C7G)

1. What Is an SDC File?

SDC (Synopsys Design Constraints) is a constraint file used by the Quartus Time Analyzer to define the timing requirements of an FPGA design.

Important:

• A design can compile without an SDC file.
• But timing will NOT be validated.
• Unconstrained paths may appear in red.

In professional FPGA development, an SDC file is mandatory.

2. When Do You Need an SDC File?

create_clock -name clk50 -period 20.000 [get_ports {MAX10_CLK1_50}]

derive_pll_clocks
derive_clock_uncertainty

set_output_delay 0.0 -clock clk_10mhz [get_ports {LEDR[*]}]

always @(posedge clk_1hz)

create_generated_clock ...

set_clock_groups -asynchronous \
    -group {clkA} \
    -group {clkB}

3. How to Use an SDC File in Quartus

Step 1 – Create a File

Create:

project.sdc

Step 2 – Add to Project

Assignments → Settings → Time Analyzer → SDC Files → Add

Or inside QSF:

set_global_assignment -name SDC_FILE project.sdc

Step 3 – Define Base Clock (MAX-10 Lite)

create_clock -name clk50 \
    -period 20.000 \
    [get_ports {MAX10_CLK1_50}]

Step 4 – Enable PLL Clock Detection

derive_pll_clocks
derive_clock_uncertainty

4. Recommended Minimal SDC for MAX-10 Lite Lab

############################################################
# MAX-10 Lite FPGA (10M50DAF484C7G)
# Recommended Minimal SDC for Teaching Labs
############################################################

# ----------------------------------------------------------
# 1) Define Primary Board Clocks
# ----------------------------------------------------------
# 10 MHz ADC clock
create_clock -name adc_clk_10 -period 100.000 [get_ports {ADC_CLK_10}]

# 50 MHz clock (typically used as system clock)
create_clock -name clk50_a    -period 20.000  [get_ports {MAX10_CLK1_50}]

# Second 50 MHz clock
create_clock -name clk50_b    -period 20.000  [get_ports {MAX10_CLK2_50}]

# ----------------------------------------------------------
# 2) Automatically Derive ALTPLL Generated Clocks
# ----------------------------------------------------------
derive_pll_clocks
derive_clock_uncertainty

# ----------------------------------------------------------
# 3) Asynchronous Push Buttons (Mechanical Inputs)
# ----------------------------------------------------------
# Treat KEY inputs as asynchronous
# (Students should use synchronizers in RTL)
set_false_path -from [get_ports {KEY[*]}]

# ----------------------------------------------------------
# 4) Constrain Board Output Devices (LED + 7-Segment)
# ----------------------------------------------------------
# Use the primary system clock (clk50_a)
# Adjust if a different system clock is used

set_output_delay 0.0 -clock clk50_a [get_ports {LEDR[*]}]

set_output_delay 0.0 -clock clk50_a [get_ports {HEX0[*]}]
set_output_delay 0.0 -clock clk50_a [get_ports {HEX1[*]}]
set_output_delay 0.0 -clock clk50_a [get_ports {HEX2[*]}]
set_output_delay 0.0 -clock clk50_a [get_ports {HEX3[*]}]
set_output_delay 0.0 -clock clk50_a [get_ports {HEX4[*]}]
set_output_delay 0.0 -clock clk50_a [get_ports {HEX5[*]}]

5. Common Red Timing Errors

Unconstrained Clocks

Clock not defined with create_clock.

Unconstrained Output Ports

No set_output_delay defined.

Illegal Clocks

Clock created from regular logic instead of PLL/global network.

6. Best Design Practice (Recommended)

Use one main clock domain.

Instead of:

always @(posedge clk_1hz)

Use:

always @(posedge clk_10mhz)
    if (tick_1hz)
        ...

This avoids creating additional clock domains and simplifies SDC.

7. How to Verify SDC Works

After compilation:

1. Tools → Time Analyzer
2. Update Timing Netlist
3. Report Clocks
4. Report Unconstrained Paths
5. Report Timing

Goal:

• All clocks detected
• Unconstrained paths = 0
• Worst-case Slack ≥ 0

8. Professional Timing Closure Flow

1. Write RTL
2. Write SDC
3. Compile
4. Check unconstrained paths
5. Analyze slack
6. Optimize if necessary

Final Summary

Board: Altera MAX-10 Lite FPGA
Device: 10M50DAF484C7G