Page 16 - EE2449_TTL_Datasheet

SN54/74LS74A

AC WAVEFORMS

D* 1.3 V 1.3 V
t h(H)
t h(L)
t s(L) t s(H)
t W(H)
t W(L)
1.3 V 1.3 V
CP
1
f MAX
t PHL
t PLH
Q
1.3 V 1.3 V
t PHL
t PLH
1.3 V 1.3 V
Q

*The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width

t W
SET
1.3 V 1.3 V

t W

CLEAR
1.3 V 1.3 V
t PLH t PHL

1.3 V 1.3 V
Q
t PHL t PLH

Q
1.3 V 1.3 V

Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths

FAST AND LS TTL DATA
5-73
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