Page 26 - EE2449_TTL_Datasheet

SN54/74LS90

SN54/74LS92
DECADE COUNTER; SN54/74LS93
DIVIDE-BY-TWELVE COUNTER;

4-BIT BINARY COUNTER

DECADE COUNTER;
The SN54/74LS90, SN54/74LS92 and SN54/74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di- DIVIDE-BY-TWELVE COUNTER;
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or 4-BIT BINARY COUNTER
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
LOW POWER SCHOTTKY
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
• Low Power Consumption ...Typically 45 mW
J SUFFIX
• High Count Rates ...Typically 42 MHz CERAMIC
• Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve, CASE 632-08
Binary 14
1
• Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES LOADING (Note a)
HIGH LOW N SUFFIX
PLASTIC
CP 0 Clock (Active LOW going edge) Input to 0.5 U.L. 1.5 U.L. CASE 646-06
÷2 Section 14
CP 1 Clock (Active LOW going edge) Input to 0.5 U.L. 2.0 U.L. 1
÷5 Section (LS90), ÷6 Section (LS92)
CP 1 Clock (Active LOW going edge) Input to 0.5 U.L. 1.0 U.L.
÷8 Section (LS93)
D SUFFIX
MR 1 , MR 2 Master Reset (Clear) Inputs 0.5 U.L. 0.25 U.L. SOIC
14
MS 1 , MS 2 Master Set (Preset-9, LS90) Inputs 0.5 U.L. 0.25 U.L. CASE 751A-02
1
Q 0 Output from ÷2 Section (Notes b & c) 10 U.L. 5 (2.5) U.L.
Q 1 , Q 2 , Q 3 Outputs from ÷5 (LS90), ÷6 (LS92), 10 U.L. 5 (2.5) U.L.
÷8 (LS93) Sections (Note b)
ORDERING INFORMATION
NOTES:
a. 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. SN54LSXXJ Ceramic
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74) SN74LSXXN Plastic
b. Temperature Ranges. SN74LSXXD SOIC
c. The Q 0 Outputs are guaranteed to drive the full fan-out plus the CP 1 input of the device.
d. To insure proper operation the rise (t r ) and fall time (t f ) of the clock must be less than 100 ns.
LOGIC SYMBOL

LS90 LS92 LS93
67
12

MS
14 CP 0 14 CP 0 14 CP 0
1 CP 1 1 CP 1 1 CP 1
MR Q 0 Q 1 Q 2 Q 3 MR Q 0 Q 1 Q 2 Q 3 MR Q 0 Q 1 Q 2 Q 3
12 1 2 12
23 12 9 8 11 6 7 12 11 9 8 23 12 9 8 11
V CC = PIN 5 V CC = PIN 5 V CC = PIN 5
GND = PIN 10 GND = PIN 10 GND = PIN 10
NC = PINS 4, 13 NC = PINS 2, 3, 4, 13 NC = PIN 4, 6, 7, 13

FAST AND LS TTL DATA
5-89
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