Page 28 - EE2449_TTL_Datasheet

SN54/74LS90 • SN54/74LS92 • SN54/74LS93

FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade, C. Divide-By-Two and Divide-By-Five Counter — No external
Divide-By-Twelve, and Binary Counters respectively. Each interconnections are required. The first flip-flop is used as a
device consists of four master/slave flip-flops which are binary element for the divide-by-two function (CP 0 as the
internally connected to provide a divide-by-two section and a input and Q 0 as the output). The CP 1 input is used to obtain
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight binary divide-by-five operation at the Q 3 output.
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
clock transition. State changes of the Q outputs do not occur LS92
simultaneously because of internal ripple delays. Therefore, A. Modulo 12, Divide-By-Twelve Counter — The CP 1 input
decoded output signals are subject to decoding spikes and must be externally connected to the Q 0 output. The CP 0 in-
should not be used for clocks or strobes. The Q 0 output of put receives the incoming count and Q 3 produces a sym-
each device is designed and specified to drive the rated metrical divide-by-twelve square wave output.
fan-out plus the CP 1 input of the device.
B. Divide-By-Two and Divide-By-Six Counter —No external
A gated AND asynchronous Master Reset (MR 1 • MR 2 ) is
interconnections are required. The first flip-flop is used as a
provided on all counters which overrides and clocks and
binary element for the divide-by-two function. The CP 1 in-
resets (clears) all the flip-flops. A gated AND asynchronous
put is used to obtain divide-by-three operation at the Q 1
Master Set (MS 1 • MS 2 ) is provided on the LS90 which
and Q 2 outputs and divide-by-six operation at the Q 3 out-
overrides the clocks and the MR inputs and sets the outputs to put.
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices LS93
may be operated in various counting modes. A. 4-Bit Ripple Counter — The output Q 0 must be externally
connected to input CP 1 . The input count pulses are applied
LS90 to input CP 0 . Simultaneous divisions of 2, 4, 8, and 16 are
A. BCD Decade (8421) Counter — The CP 1 input must be ex- performed at the Q 0 , Q 1 , Q 2 , and Q 3 outputs as shown in
ternally connected to the Q 0 output. The CP 0 input receives the truth table.
the incoming count and a BCD count sequence is pro-
B. 3-Bit Ripple Counter— The input count pulses are applied
duced.
to input CP 1 . Simultaneous frequency divisions of 2, 4, and
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q 3 8 are available at the Q 1 , Q 2 , and Q 3 outputs. Independent
output must be externally connected to the CP 0 input. The use of the first flip-flop is available if the reset function coin-
input count is then applied to the CP 1 input and a divide-by- cides with reset of the 3-bit ripple-through counter.
ten square wave is obtained at output Q 0 .

FAST AND LS TTL DATA
5-91
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